1. Field of the Invention
The invention relates to a semiconductor device, and in particular to an on-chip inductor with a multi-level interconnect structure.
2. Description of the Related Art
Many digital and analog elements and circuits have been successfully applied in semiconductor integrated circuits. Such elements may include passive components, such as resistors, capacitors, or inductors. Typically, a semiconductor integrated circuit is formed on a silicon substrate. One or more dielectric layers are disposed on the substrate and one or more conductive layers are disposed in the dielectric layers. Those conductive layers may be employed to form on-chip elements, such as on-chip inductors, by current semiconductor technologies.
Conventionally, the on-chip inductor is formed over a semiconductor substrate and employed in integrated circuits designed for radio frequency (RF) band. FIGS. 1A and 1B illustrate a plan view of a conventional on-chip inductor with a planar spiral configuration and a cross-section along 1B-1B′ line shown in FIG. 1A, respectively. The on-chip inductor is formed in a dielectric layer 104 on a substrate 100, comprising a spiral conductive trace 103 and an interconnect structure. The interconnect structure includes conductive plugs 105 and 109 and a conductive trace 107 embedded in a dielectric layer 102 and a conductive trace 111 embedded in the dielectric layer 104. The conductive trace 107, the dielectric layer 102, conductive plugs 105 and 109, the conductive trace 103, and the dielectric layer 104 are sequentially formed on the substrate 100. An internal circuit of the chip or an external circuit may provides a current passing through the coil, which includes the conductive trace 103, the conductive plug 105, the conductive trace 107, the conductive plug 109, and the meal trace 111, and utilize the inductance induced by the coil.
A principle advantage of the planar spiral inductor is increased level of the integration for the circuit due to reduced circuit elements located off the chip along with attendant need for complex interconnections. Moreover, the planar spiral inductor can reduce parasitic effect induced by the bond pads or bond wires between on-chip and off-chip circuits. The planar spiral inductor, however, is limited by the space for configuration of the spiral conductive trace 103 and the interval S of the neighboring regions of the spiral conductive trace 103. Thus, it is difficult to decrease the size d1 of the planar spiral inductor. That is, the planar spiral inductor occupies a larger area of the chip, making it difficult to increase the integration and reduce manufacturing cost.
To decrease the size of the on-chip inductor, it has been suggested to form the inductor with solenoid structure, as shown in FIGS. 2A and 2B, a plan view of a conventional on-chip inductor with a solenoid structure and a cross-section along 2B-2B′ line shown in FIG. 2A, respectively. The solenoid inductor has an upper conductive trace 203 and an overlapping lower conductive trace 209. The lower conductive trace 209 is embedded in a dielectric layer 202 on a substrate 200. The upper conductive trace 203 is embedded in a dielectric layer 204 on the dielectric layer 202. The upper conductive trace 203 has a gap g1 to define a first end 50 and a second end 52, electrically connecting to the lower conductive trace 209 by a conductive plug 205 embedded in the dielectric layer 202 and adjacent to the second end 52 of the upper conductive trace 203. An internal circuit of the chip or an external circuit may provides a current passing through the coil, which includes the conductive trace 203, the conductive plug 205, the conductive trace 209, the conductive plug 207, and the meal trace 211, and utilize the inductance induced by the coil.
The multilayer winding inductor has a solenoid structure, thus its size d2 is relatively smaller than the planar spiral inductor mentioned and can occupy a smaller area of the chip. The lower conductive trace 209, however, has a thickness less than the upper conductive trace 203 formed by an uppermost conductive layer due to the restrictions of manufacturing process. Therefore, the series resistance of the overlap winding inductor is increased, resulting in reduction of the quality factor (Q value) and a lower Q value compared to the planar spiral inductor.
Since the integrated circuit device performance is based on the size and the Q value of the on-chip inductor, there is a need to develop an improved on-chip inductor with decreased size and retained Q value thereof.